High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims     

Link budget analysis for multistandard receiver architectures

As devices shrink, creating integrated circuits (ICs) that work with the required accuracy becomes more difficult due to issues related to device physics. Receivers are part of an area referred to as "mixed-signal design," meaning that both analog and digital circuitry will be on the same IC. This too presents many challenging issues, as the analog circuitry is highly sensitive to disruptions caused by the noisy digital circuitry. Therefore, accurate modeling and simulation is crucial in the design of wireless receivers to ensure the best possible operation of the fabricated IC. Through simulation and modeling a designer can determine if receiver architecture will meet the required specifications and pinpoint the possible problems before valuable time is spent developing the actual circuit. This article will present design issues for multistandard wireless receivers to give the reader an understanding of the challenges involved in link-budget analysis. TITAN (Toolbox for Integrated Transceiver Analysis), a link-budget analysis tool developed at The Ohio State University Analog VLSI Laboratory, will be presented as an example of a tool for receiver simulation. To determine design performance, various requirements must be translated to model parameters. Among the requirements for receivers are noise floor (NF), second- and third-order distortion (IP2 and IP3, respectively), reciprocal mixing, and phase noise. TITAN offers a graphical interface and encapsulated models to the designer, eliminating the possibility of formula corruption. The interface provides a more intuitive and sophisticated way of setting up the simulation and provides the designer with more readable results. Additionally, a blocking profile component allows the architecture to be tested across multiple standards.     

Statistical modeling of device mismatch for analog MOS integratedcircuits

A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms     

CMOS low-power bandpass IF filter for Bluetooth

Design of a CMOS 18th-order IF (intermediate frequency) bandpass filter for integrated low-IF Bluetooth receivers is presented. The centre frequency and bandwidth of the filter are 3 and 1 MHz, respectively. The proposed filter is based on unity gain fully differential voltage buffers and provides efficient, low power and a small area design solution. The filter, including its automatic tuning circuit, occupies an area of 0.6 mm² in a standard 0.5 mum-CMOS chip. Experimental results show that the filter satisfies the selectivity and dynamic range requirements of Bluetooth while operating from a total supply current of 0.9 mA     

High-transconductance n-type Si/SiGe modulation-doped field-effecttransistors

The authors report on the fabrication and the resultant device characteristics of the first 0.25-μm gate-length field-effect transistor based on n-type modulation-doped Si/SiGe. Prepared using ultrahigh vacuum/chemical vapor deposition (UHV/CVD), the mobility and electron sheet charge density in the strained Si channel are 1500 (9500) cm²/V-s and 2.5×10¹² (1.5×10¹² ) cm^-2 at 300 K (77 K). At 77 K, the devices have a current and transconductance of 325 mA/mm and 600 mS/mm, respectively. These values far exceed those found in Si MESFETs and are comparable to the best results achieved in GaAs/AlGaAs modulation-doped transistors     

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling     

The Bivariate Transmuted Family of Distributions: Theory and Applications

The bivariate distributions are useful in simultaneous modeling of two random variables. These distributions provide a way to model models. The bivariate families of distributions are not much widely explored and in this article a new family of bivariate distributions is proposed. The new family will extend the univariate transmuted family of distributions and will be helpful in modeling complex joint phenomenon. Statistical properties of the new family of distributions are explored which include marginal and conditional distributions, conditional moments, product and ratio moments, bivariate reliability and bivariate hazard rate functions. The maximum likelihood estimation (MLE) for parameters of the family is also carried out. The proposed bivariate family of distributions is studied for the Weibull baseline distributions giving rise to bivariate transmuted Weibull (BTW) distribution. The new bivariate transmuted Weibull distribution is explored in detail. Statistical properties of the new BTW distribution are studied which include the marginal and conditional distributions, product, ratio and conditional momenst. The hazard rate function of the BTW distribution is obtained. Parameter estimation of the BTW distribution is also done. Finally, real data application of the BTW distribution is given. It is observed that the proposed BTW distribution is a suitable fit for the data used.     

Novel hybrid DNN approaches for speaker verification in emotional and stressful talking environments

Neural Computing and Applications - In this work, we conducted an empirical comparative study of the performance of text-independent speaker verification in emotional and stressful environments....